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information in this document is provided solely to enable use of intel products. intel assumes no lia bility whatsoever, including infringe- ment of any patent or copyright, for sale and use of intel produ cts except as provided in intels terms and conditions of sale for such products. information contained herein supersedes previously published specifications on these devices from intel. ? intel corporation, 1995 o ctober 1995 8xc196np commercial chmos 16-bit microcontroller the 8xc196np is a member of intels 16-bit mcs ? 96 microcontroller family. the device features 1 mbyte of linear address space, a demultiplexed bus, and a chip-select unit. the external bus can dynamically switch between multiplexed and demultiplexed operation. when operating at 25 mhz in demultiplexed mode, the 8xc196np can access a 100 ns memory device with zero wait states. the 8xc196np is available without rom (80c196np) or with 4 kbytes of rom (83c196np). n 25 mhz operation at 4.5C5.5 volts n 1 mbyte of linear address space n optional 4 kbytes of rom n 1000 bytes of register ram n register-register architecture n 32 i/o port pins n 16 prioritized interrupt sources n 4 external interrupt pins and nmi pin n 2 flexible 16-bit timer/counters with quadrature counting capability n 3 pulse-width modulator (pwm) outputs with high drive capability n full-duplex serial port with dedicated baud-rate generator n peripheral transaction server n event processor array (epa) with 4 high-speed capture/compare channels n chip-select unit 6 chip select pins dynamic demulti plexed/multi- plexed address/data bus for each chip select programmable wait states (0, 1, 2, or 3) for each chip select programmable bus width (8- or 16- bit) for each chip select programmable address range for each chip select n 1.12 m s 16 16 unsigned multiplication n 1.92 m s 32/16 unsigned division n 100-pin sqfp or 100-pin qfp pa ckage n complete system development support n high-speed chmos technology order number: 27245 9-005
8xc196np commercial chmos 16-bit microcontroller 2 figure 1. 8xc196np block diagram timer 1 timer 2 event processor array serial port baud rate gen port 2 port 1 port 1/ epa3:0, timer 1, timer 2 port 2/ hold control, sio, extint1:0 pulse width modulator microcode engine ralu cpu peripheral transaction server 4k bytes rom (optional) ad15:0 a15:0 a19:16/ eport3:0 chip select cs5:0# interrupt controller 16 16 8 1000 byte register file 24 bytes cpu sfrs memory controller with chip select queue port 3 port 4 port 3/ extint3:2 port 4/ pwm2:0 a2351-01 control signals
8xc196np commercial chmos 16-bit microcontroller 3 process information this device is manufactured on p648, a chmos iv process. additional process and reliability infor- mation is available in intels components quality and reliability handbook (order number 210997). all thermal impedance data is approximate for static air conditions at 1 watt of power dissipation. values will change depending on operating conditions and the application. the intel packaging handbook (order number 240800) describes intels thermal impedance test methodology. table 1. thermal characteristics package type q ja q jc 100-pin sqfp 55 c/w 14 c/w 100-pin qfp 56 c/w 16 c/w figure 2. the 8xc196np family nomenclature table 2. description of product nomenclature parameter options description temperature and burn-in options no mark commercial operating temperature range (0c to 70c) with intel standard burn-in. packaging options s sb qfp sqfp programCmemory options 0 3 no rom rom process information c chmos product family 196np device speed no mark 25 mhz program-memory options xxxxx xx x x 8 xx x packaging options temperature and burn-in options a2815-01 process information product family device speed
8xc196np commercial chmos 16-bit microcontroller 4 table 3. 8xc196np memory map address (note 1) description notes ff ffffh ff 3000h external device (memory or i/o) connected to address/data bus 9 ff 2fffh ff 2000h internal rom or external device (memory or i/o) connected to address/data bus (determined by ea# pin) 2,9 ff 1fffh ff 0000h external device (memory or i/o) connected to address/data bus 3,9 fe ffffh 0f 0000h overlaid memory (reserved for future devices) 3,9 0e ffffh 01 0000h 896 kbytes of external device (memory or i/o) connected to address/data bus 9 00 ffffh 00 3000h external device (memory or i/o) connected to address/data bus 9 00 2fffh 00 2000h external device (memory or i/o) connected to address/data bus or remapped internal rom 5, 6,9 00 1fffh 00 1fe0h memory-mapped peripheral special-function registers (sfrs) 4, 7,9 00 1fdfh 00 1f00h internal peripheral special-function registers (sfrs) 4, 7, 10 00 1effh 00 0400h external device (memory or i/o) (reserved for future devices) 6 00 03ffh 00 0100h upper register file (general-purpose register ram) 8, 10 00 00ffh 00 0018h lower register file (general-purpose register ram and stack pointer) 8, 11 00 0017h 00 0000h lower register file (cpu sfrs) 4, 7, 8, 11 notes: 1. internally, there are 24 address bits (a23:0); however, only 20 address lines (a19:0) are bonded out. the external address space is 1 mbyte (00000Cfffffh). 2. the 8xc196np resets to internal address ff2080h (ff2080h in internal rom or f2080h in external memory). 3. do not locate code in addresses x f0000C x f00ffh. these addresses are reserved for the ice in-cir- cuit emulator. unless otherwise noted, write 0ffh to reserved memory locations. 4. unless otherwise noted, write 0 to reserved sfr bits. 5. these areas are mapped into internal rom if the remap bit (ccb1.2) is set and ea# is at logic 1. otherwise, they are mapped to external memory. 6. warning : the contents or functions of these memory locations may change with future device revi- sions, in which case a program that relies on one or more of these locations may not function properly. 7. refer to the 8xc196np users manual or 8xc196np quick reference for sfr descriptions. 8. code executed in locations 000000h to 0003ffh will be forced external. 9. address with indirect, indexed, or extended modes. 10. address with indirect, indexed, or extended modes or through register windows. 11. address with direct, indirect, indexed, or extended modes.
8xc196np commercial chmos 16-bit microcontroller 5 figure 3. 8xc196np 100-pin sqfp package rd# bhe# / wrh# ale inst ready rpd once v ss v cc v ss a8 a9 a10 a11 a12 a13 a14 a15 nc v ss xtal1 xtal2 v ss nc p2.7 / clkout ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 v cc ad8 v ss ad9 ad10 ad11 ad12 ad13 ad14 ad15 a16 / eport.0 a17 / eport.1 v cc v ss a18 / eport.2 a19 / eport.3 wr# / wrl# a2348-04 reset# nmi ea# a0 a1 v cc v ss a2 a3 a4 a5 a6 a7 v cc v ss nc nc p3.0 / cs0# p3.1 / cs1# p3.2 / cs2# p3.3 / cs3# v ss p3.4 / cs4# p3.5 / cs5# p3.6 / extint2 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 sb8xc196np view of component as mounted on pc board 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 p3.7 / extint3 p1.0 / epa0 v cc p1.1 / epa1 p1.2 / epa2 p1.3 / epa3 p1.4 / t1clk p1.5 / t1dir v cc p1.6 / t2clk v ss p1.7 / t2dir p4.0 / pwm0 p4.1 / pwm1 p4.2 / pwm2 p4.3 v cc v ss p2.0 / txd p2.1 / rxd p2.2 / extint0 p2.3 / breq# p2.4 / extint1 p2.5 / hold# p2.6 / hlda# 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
8xc196np commercial chmos 16-bit microcontroller 6 table 4. 8xc196np 100-pin sqfp pin assignment pin name pin name pin name pin name 1 reset# 26 extint3/p3.7 51 clkout/p2.7 76 wr#/wrl# 2 nmi 27 epa0/p1.0 52 nc ? 77 eport.3/a19 3ea# 28v cc 53 v ss 78 eport.2/a18 4 a0 29 epa1/p1.1 54 xtal2 79 v ss 5 a1 30 epa2/p1.2 55 xtal1 80 v cc 6v cc 31 epa3/p1.3 56 v ss 81 eport.1/a17 7v ss 32 t1clk/p1.4 57 nc ? 82 eport.0/a16 8 a2 33 t1dir/p1.5 58 a15 83 ad15 9a3 34v cc 59 a14 84 ad14 10 a4 35 t2clk/p1.6 60 a13 85 ad13 11 a5 36 v ss 61 a12 86 ad12 12 a6 37 t2dir/p1.7 62 a11 87 ad11 13 a7 38 pwm0/p4.0 63 a10 88 ad10 14 v cc 39 pwm1/p4.1 64 a9 89 ad9 15 v ss 40 pwm2/p4.2 65 a8 90 v ss 16 nc ? 41 p4.3 66 v ss 91 ad8 17 nc ? 42 v cc 67 v cc 92 v cc 18 cs0#/p3.0 43 v ss 68 v ss 93 ad7 19 cs1#/p3.1 44 txd/p2.0 69 once 94 ad6 20 cs2#/p3.2 45 rxd/p2.1 70 rpd 95 ad5 21 cs3#/p3.3 46 extint0/p2.2 71 ready 96 ad4 22 v ss 47 breq#/p2.3 72 inst 97 ad3 23 cs4#/p3.4 48 extint1/p2.4 73 ale 98 ad2 24 cs5#/p3.5 49 hold#/p2.5 74 bhe#/wrh# 99 ad1 25 extint2/p3.6 50 hlda#/p2.6 75 rd# 100 ad0 ? to be compatible with future versions of the n x family, tie the no connection (nc) pins as follows: pin 57 = v ss , pin 16 = v cc , pin 17 = v ss (5 volts on this pin will enable a clock doubler on future devices), and pin 52 = v cc .
8xc196np commercial chmos 16-bit microcontroller 7 table 5. 100-pin sqfp pin assignment arranged by functional categories address & data address & data (cont) input/output power & ground name pin name pin name pin name pin a0 4 ad13 85 cs0#/p3.0 18 v cc 6 a1 5 ad14 84 cs1#/p3.1 19 v cc 14 a2 8 ad15 83 cs2#/p3.2 20 v cc 28 a3 9 cs3#/p3.3 21 v cc 34 a4 10 bus control & status cs4#/p3.4 23 v cc 42 a5 11 name pin cs5#/p3.5 24 v cc 67 a6 12 ale 73 epa0/p1.0 27 v cc 80 a7 13 bhe#/wrh# 74 epa1/p1.1 29 v cc 92 a8 65 breq# 47 epa2/p1.2 30 v ss 7 a9 64 hold# 49 epa3/p1.3 31 v ss 15 a10 63 hlda# 50 eport.0 82 v ss 22 a11 62 inst 72 eport.1 81 v ss 36 a12 61 rd# 75 eport.2 78 v ss 43 a13 60 ready 71 eport.3 77 v ss 53 a14 59 wr#/wrl# 76 p2.2 46 v ss 56 a15 58 p2.3 47 v ss 66 a16 82 processor control p2.4 48 v ss 68 a17 81 name pin p2.5 49 v ss 79 a18 78 clkout 51 p2.6 50 v ss 90 a19 77 ea# 3 p2.7 51 ad0 100 extint0 46 p3.6 25 no connection ad1 99 extint1 48 p3.7 26 name pin ad2 98 extint2 25 p4.3 41 nc 16 ad3 97 extint3 26 pwm0/p4.0 38 nc 17 ad4 96 nmi 2 pwm1/p4.1 39 nc 52 ad5 95 once 69 pwm2/p4.2 40 nc 57 ad6 94 reset# 1 rxd/p2.1 45 ad7 93 rpd 70 t1clk/p1.4 32 ad8 91 xtal1 55 t1dir/p1.5 33 ad9 89 xtal2 54 t2clk/p1.6 35 ad10 88 t2dir/p1.7 37 ad11 87 txd/p2.0 44 ad12 86
8xc196np commercial chmos 16-bit microcontroller 8 figure 4. 8xc196np 100-pin qfp package v ss a18 / eport.2 a19 / eport.3 wr# / wrl# rd# bhe# / wrh# ale inst ready rpd once v ss v cc v ss a8 a9 a10 a11 a12 a13 a14 a15 v ss xtal1 xtal2 v ss p2.7 / clkout nc p2.6 / hlda# p2.5 / hold# ad1 ad2 ad3 ad4 ad5 ad6 ad7 v cc ad8 v ss ad9 ad10 ad11 ad12 ad13 ad14 ad15 a16 / eport.0 a17 / eport.1 v cc a2349-03 ad0 nc reset# nmi ea# a0 a1 v cc v ss a2 a3 a4 a5 a6 a7 v cc v ss nc p3.0 / cs0# p3.1 / cs1# p3.2 / cs2# p3.3 / cs3# v ss p3.4 / cs4# p3.5 / cs5# p3.6 / extint2 nc p3.7 / extint3 p1.0 / epa0 v cc 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 s8xc196np view of component as mounted on pc board 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 p1.1 / epa1 p1.2 / epa2 p1.3 / epa3 p1.4 / t1clk p1.5 / t1dir v cc p1.6 / t2clk v ss p1.7 / t2dir p4.0 / pwm0 p4.1 / pwm1 p4.2 / pwm2 p4.3 v cc v ss p2.0 / txd p2.1 / rxd p2.2 / extint0 p2.3 / breq# p2.4 / extint1 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
8xc196np commercial chmos 16-bit microcontroller 9 table 6. 8xc196np 100-pin qfp pin assignment pin name pin name pin name pin name 1 ad0 26 extint2/p3.6 51 hold#/p2.5 76 rd# 2 no connection 27 no connection 52 hlda#/p2.6 77 wr#/wrl# 3 reset# 28 extint3/p3.7 53 no connection 78 eport.3/a19 4 nmi 29 epa0/p1.0 54 clkout/p2.7 79 eport.2/a18 5ea# 30v cc 55 v ss 80 v ss 6 a0 31 epa1/p1.1 56 xtal2 81 v cc 7 a1 32 epa2/p1.2 57 xtal1 82 eport.1/a17 8v cc 33 epa3/p1.3 58 v ss 83 eport.0/a16 9v ss 34 t1clk/p1.4 59 a15 84 ad15 10 a2 35 t1dir/p1.5 60 a14 85 ad14 11 a3 36 v cc 61 a13 86 ad13 12 a4 37 t2clk/p1.6 62 a12 87 ad12 13 a5 38 v ss 63 a11 88 ad11 14 a6 39 t2dir/p1.7 64 a10 89 ad10 15 a7 40 pwm0/p4.0 65 a9 90 ad9 16 v cc 41 pwm1/p4.1 66 a8 91 v ss 17 v ss 42 pwm2/p4.2 67 v ss 92 ad8 18 no connection 43 p4.3 68 v cc 93 v cc 19 cs0#/p3.0 44 v cc 69 v ss 94 ad7 20 cs1#/p3.1 45 v ss 70 once 95 ad6 21 cs2#/p3.2 46 txd/p2.0 71 rpd 96 ad5 22 cs3#/p3.3 47 rxd/p2.1 72 ready 97 ad4 23 v ss 48 extint0/p2.2 73 inst 98 ad3 24 cs4#/p3.4 49 breq#/p2.3 74 ale 99 ad2 25 cs5#/p3.5 50 extint1/p2.4 75 bhe#/wrh# 100 ad1
8xc196np commercial chmos 16-bit microcontroller 10 table 7. 100-pin qfp pin assignment arranged by functional categories address & data address & data (cont) input/output power & ground name pin name pin name pin name pin a0 6 ad13 86 cs0#/p3.0 19 v cc 8 a1 7 ad14 85 cs1#/p3.1 20 v cc 16 a2 10 ad15 84 cs2#/p3.2 21 v cc 30 a3 11 cs3#/p3.3 22 v cc 36 a4 12 bus control & status cs4#/p3.4 24 v cc 44 a5 13 name pin cs5#/p3.5 25 v cc 68 a6 14 ale 74 epa0/p1.0 29 v cc 81 a7 15 bhe#/wrh# 75 epa1/p1.1 31 v cc 93 a8 66 breq# 49 epa2/p1.2 32 v ss 9 a9 65 hold# 51 epa3/p1.3 33 v ss 17 a10 64 hlda# 52 eport.0 83 v ss 23 a11 63 inst 73 eport.1 82 v ss 38 a12 62 rd# 76 eport.2 79 v ss 45 a13 61 ready 72 eport.3 78 v ss 55 a14 60 wr#/wrl# 77 p2.2 48 v ss 58 a15 59 p2.3 49 v ss 67 a16 83 processor control p2.4 50 v ss 69 a17 82 name pin p2.5 51 v ss 80 a18 79 clkout 54 p2.6 52 v ss 91 a19 78 ea# 5 p2.7 54 ad0 1 extint0 48 p3.6 26 no connection ad1 100 extint1 50 p3.7 28 name pin ad2 99 extint2 26 p4.3 43 nc 2 ad3 98 extint3 28 pwm0/p4.0 40 nc 18 ad4 97 nmi 4 pwm1/p4.1 41 nc 27 ad5 96 once 70 pwm2/p4.2 42 nc 53 ad6 95 reset# 3 rxd/p2.1 47 ad7 94 rpd 71 t1clk/p1.4 34 ad8 92 xtal1 57 t1dir/p1.5 35 ad9 90 xtal2 56 t2clk/p1.6 37 ad10 89 t2dir/p1.7 39 ad11 88 txd/p2.0 46 ad12 87
8xc196np commercial chmos 16-bit microcontroller 11 pin descriptions table 8. pin descriptions name type description multiplexed with a15:0 i/o system address bus these address lines provide address bits 0C15 during the en tire external memory cycle during both multiplexed and demultiplexed bus modes. a19:16 i/o address lines 16C19 these address lines provide address bits 16C19 during the entire external memory cycle, supporting extended addressing of the 1- mbyte address space. internally, there are 24 address bits; however, only 20 address lines (a19:0) are bonded out. the external address space is 1 mbyte (00000Cfffffh) and the internal address space is 16 mbytes (000000Cffffffh). the 8xc196np resets to internal address ff2080h (ff2080h in internal rom or f2080h in external memory). eport.3:0 ad15:0 i/o address/data lines the function of these pins depends on the bus size and mode. 16-bit multiplexed bus mode : ad15:0 drive address bits 0C15 during the first half of the bus cycle and drive or receive data during the second half of the bus cycle. 8-bit multiplexed bus mode : ad15:8 drive address bits 8C15 during the en tire bus cycle. ad7:0 drive add ress b its 0C7 during the first half of the bus cycle and drive or receive data during the second half of the bus cycle. 16-bit demultiplexed mode : ad15:0 drive or receive data during the entire bus cycle. 8-bit demultiplexed mode : ad7:0 drive or receive data during the entire bus cycle. ad15:8 drive the data that is currently on the high byte of the internal bus. ale o address latch enable this active-high output signal is asserted only during external memory cycles. ale signals the start of an external bus cycle and indicates that valid address information is available on the system address/data bus (a19:16 and ad15:0 for a multiplexed bus; a19:0 for a demultiplexed bus). ale differs from adv# in that it does not remain active during the entire bus cycle. an external latch can use this signal to demultiplex the address bits 0C15 from the address/data bus in multiplexed mode.
8xc196np commercial chmos 16-bit microcontroller 12 bhe# o byte high enable the chip configuration register 0 (ccr0) determines whether this pin functions as bhe# or wrh#. ccr0.2=1 selects bhe#; ccr0.2=0 selects wrh#. during 16-bit bus cycles, this active-low output signal is asserted for word reads and writes and high-byte reads and writes to external memory. bhe# indicates that valid data is being transferred over the upper half of the system data bus. use bhe#, in conjunction with a0, to determine which memory byte is being transferred over the system bus: bhe# a0 byte(s) accessed 0 0 both bytes 0 1 high byte only 1 0 low byte only wrh# breq# o bus request this active-low output signal is asserted during a hold cycle when the bus controller has a pending external memory cycle. the device can assert breq# at the same time as or after it asserts hlda#. once it is asserted, breq# remains asserted until hold# is removed. you must enable the bus-hold protocol before using this signal. p2.3 clkout o clock output output of the internal clock generator. the clkout frequency is ? the internal operating frequency (f xtal 1 ). clkout has a 50% duty cycle. p2.7 cs5#:0 o chip-select lines 0C5 the active-low output cs x # is asserted during an external memory cycle when the address to be accessed is in the range programmed for chip select x . if the external memory address is outside the range assigned to the six chip selects, no chip-select output is asserted and the bus configuration defaults to the cs5# values. immediately following reset, cs0# is automatically assigned to the range ff2000Cff20ffh (f2000Cf20ffh if external). p3.5:0 ea# i external access this input determines whether memory accesses to special- purpose and program memory partitions (ff2000Cff2fffh) are directed to internal or external memory. these accesses are directed to internal memory if ea# is held high and to external memory if ea# is held low. for an access to any other memory location, the value of ea# is irrelevant. ea# is not latched and can be switched dynamically during normal operating mode. be sure to thoroughly consider the issues, such as different access times for internal and external memory, before using this dynamic switching capability. on devices with no internal nonvolatile memory, always connect ea# to v ss . table 8. pin descriptions (continued) name type description multiplexed with
8xc196np commercial chmos 16-bit microcontroller 13 epa3:0 i/o event processor array (epa) input/output pins these are the high-speed input/output pins for the epa capture/compare channels. for high-speed pwm applications, the outputs of two epa channels (either epa0 and epa1 or epa2 and epa3) can be remapped to produce a pwm waveform on a shared output pin. p1.3:0 eport.3:0 i/o extended addressing port this is a 4-bit, bidirectional, memory-mapped i/o port. the pins are shared with the extended address bus a19:16. a19:16 extint0 extint1 extint2 extint3 i external interrupts in normal operating mode, a rising edge on extint x sets the extint x interrupt pending bit. extint x is sampled during phase 2 (clkout high). the minimum high time is one state time. in powerdown mode, asserting the extint x signal for at least 1 state time causes the device to resume normal operation. the interrupt need not be enabled, but the pin must be configured as a special-function input. if the extint x interrupt is enabled, the cpu executes the interrupt service routine. otherwise, the cpu executes the instruction that immediately follows the command that invoked the power-saving mode. in idle mode, asserting any enabled interrupt causes the device to resume normal operation. p2.2 p2.4 p3.6 p3.7 hlda# o bus hold acknowledge this active-low output indicates that the cpu has released the bus as the result of an external device asserting hold#. p2.6 hold# i bus hold request an external device uses this active-low input signal to request control of the bus. this pin functions as hold# only if the pin is configured for its special function and the bus-hold protocol is enabled. setting bit 7 of the window selection register enables the bus-hold protocol. p2.5 inst o instruction fetch this active-high output signal is valid only during external memory bus cycles. when high, inst indicates that an instruction is being fetched from external memory. the signal remains high during the entire bus cycle of an external instruction fetch. inst is low for data accesses, including interrupt vector fetches and chip configuration byte reads. inst is low during internal memory fetches. nmi i nonmaskable interrupt in normal operating mode, a rising edge on nmi generates a nonmaskable interrupt. nmi has the highest priority of all prioritized interrupts. assert nmi for greater than one state time to guarantee that it is recognized. table 8. pin descriptions (continued) name type description multiplexed with
8xc196np commercial chmos 16-bit microcontroller 14 once i on-circuit emulation holding once high during the rising edge of reset# places the device into on-circuit emulation (once) mode. this mode puts all pins into a high-impedance state, thereby isolating the device from other components in the system. the value of once is latched when the reset# pin goes inactive. while the device is in once mode, you can debug the system using a clip-on emulator. to exit once mode, reset the device by pulling the reset# signal low. to prevent accidental entry into once mode, connect the once pin to v ss . p1.3:0 p1.4 p1.5 p1.6 p1.7 i/o port 1 this is a standard, bidirectional port that is multiplexed with individ- ually selectable special-function signals. epa3:0 t1clk t1dir t2clk t2dir p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 i/o port 2 this is a standard, bidirectional port that is multiplexed with individ- ually selectable special-function signals. txd rxd extint0 breq# extint1 hold# hlda# clkout p3.5:0 p3.6 p3.7 i/o port 3 this is an 8-bit, bidirectional, standard i/o port. cs5:0# extint2 extint3 p4.2:0 p4.3 i/o port 4 this is a 4-bit, bidirectional, standard i/o port with high-current drive capability. pwm2:0 pwm2:0 o pulse width modulator outputs these are pwm output pins with high-current drive capability. the duty cycle and frequency-pulse-widths are programmable. p4.2:0 rd# o read read-signal output to external memory. rd# is asserted only during external memory reads. ready i ready input this active-high input signal is used to lengthen external memory cycles for slow memory by generating wait states in addition to the wait states that are generated internally. when ready is high, cpu operation continues in a normal manner with wait states inserted as programmed in the chip configuration registers, register 0, or the chip-select x bus control register. ready is ignored for all internal memory accesses. table 8. pin descriptions (continued) name type description multiplexed with
8xc196np commercial chmos 16-bit microcontroller 15 reset# i/o reset a level-sensitive reset input to and open-drain system reset output from the microcontroller. either a falling edge on reset# or an internal reset turns on a pull-down transistor connected to the reset# pin for 16 state times. in the powerdown, standby, and idle modes, asserting reset# causes the chip to reset and return to normal operating mode. after a device reset, the first instruction fetch is from ff2080h (or f2080h in external memory). for the 80c196np, the program and special-purpose memory locations (ff2000Cff2fffh) reside in external memory. for the 83c196np, these locations can reside either in external memory or in internal rom. rpd i return from powerdown timing pin for the return-from-powerdown circuit. if your application uses powerdown mode, connect a capacitor between rpd and v ss if the internal oscillator is the clock source. the capacitor causes a delay that enables the oscillator to stabilize before the internal cpu and peripheral cl ocks are enabled. the capacitor is not required if your application uses powerdown mode and if an external clock input is the clock source. if your application does not use powerdown mode, leave this pin unconnected. rxd i/o receive serial data in modes 1, 2, and 3, rxd receives serial port input data. in mode 0, it functions as either an input or an open-drain output for data. p2.1 t1clk i timer 1 external clock external clock for timer 1. timer 1 increments (or decrements) on both rising and falling edges of t1clk. also used in conjunction with t1dir for quadrature counting mode. and external clock for the serial i/o baud-rate generator input (program selectable). p1.4 t2clk i timer 2 external clock external clock for timer 2. timer 2 increments (or decrements) on both rising and falling edges of t2clk. also used in conjunction with t2dir for quadrature counting mode. p1.6 t1dir i timer 1 external direction external direction (up/down) for timer 1. timer 1 increments when t1dir is high and decrements when it is low. also used in conjunction with t1clk for quadrature counting mode. p1.5 t2dir i timer 2 external direction external direction (up/down) for timer 2. timer 2 increments when t2dir is high and decrements when it is low. also used in conjunction with t2clk for quadrature counting mode. p1.7 table 8. pin descriptions (continued) name type description multiplexed with
8xc196np commercial chmos 16-bit microcontroller 16 electrical characteristics txd o transmit serial data in serial i/o modes 1, 2, and 3, txd is used to transmit serial port data. in mode 0, it is used as the serial clock output. p2.0 v cc pwr digital supply voltage connect each v cc pin to the digital supply voltage. v ss gnd digital circuit ground connect each v ss pin to ground through the lowest possible impedance path. wr# o write this active-low output indicates that an external write is occurring. this signal is asserted only during external memory writes. the chip configuration register 0 (ccr0) determines whether this pin functions as wr# or wrl#. ccr0.2=1 selects wr#; ccr0.2=0 selects wrl#. wrl# wrh# o write high during 16-bit bus cycles, this active-low output signal is asserted for high-byte writes and word writes to external memory. during 8-bit bus cycles, wrh# is asserted for all write operations. the chip configuration register 0 (ccr0) determines whether this pin functions as bhe# or wrh#. ccr0.2=1 selects bhe#; ccr0.2=0 selects wrh#. bhe# wrl# o write low during 16-bit bus cycles, this active-low output signal is asserted for low-byte writes and word writes. during 8-bit bus cycles, wrl# is asserted for all write operations. the chip configuration register 0 (ccr0) determines whether this pin functions as wr# or wrl#. ccr0.2=1 selects wr#; ccr0.2=0 selects wrl#. wr# xtal1 i input crystal/resonator or external clock input input to the on-chip oscillator and the internal clock generators. the internal clock generators provide the peripheral cl ocks, cpu clock, and clkout signal. when using an external clock source instead of the on-chip oscillator, connect the clock input to xtal1. the external clock signal must meet the v ih specification for xtal1. xtal2 o inverted output for the crystal/resonator output of the on-chip oscillator inverter. leave xtal2 floating when the design uses an external clock source instead of the on-chip oscillator. table 8. pin descriptions (continued) name type description multiplexed with
8xc196np commercial chmos 16-bit microcontroller 17 absolute maximum ratings* storage temperature .................................. C60c to +150c supply voltage with respect to v ss .............. C0.5 v to +7.0 v power dissipation .......................................................... 1.5 w operating conditions* t a (ambient temperature under bias)................ 0c to +70c v cc (digital supply voltage) ............................. 4.5 v to 5.5 v f xtal 1 (input frequency for v cc = 4.5C5.5 v) (note 1) ................................................. 8 mhz to 25 mhz notes: 1. this device is static and should operate below 1 hz, but has been tested only down to 8 mhz. notice : this document contains information on products in the design phase of development. the specifications are subject to change without notice. do not finalize a design with this information. revised information will be published when the product is available. verify with your local intel sales office that you have the latest datasheet before finalizing a design. * warning : stressing the device beyond the absolute maximum ratings may cause permanent damage. these are stress ratings only. operation beyond the operating conditions is not reco mmended and extended exposure beyond the operating conditions may affect device reli- ability.
8xc196np commercial chmos 16-bit microcontroller 18 dc characteristics table 9. dc characteristics at v cc = 4.5 C 5.5 v (note 1) symbol parameter min ty p max units test conditions i cc v cc supply current 80 120 ma xtal1 = 25 mhz v cc = 5.5 v device in reset i idle idle mode current 24 36 ma xtal1 = 25 mhz v cc = 5.5 v i pd powerdown mode current (note 2) 50 75 a v cc = 5.5 v i li input leakage current (all input pins except reset) 10 a v ss < v in < v cc v il input low voltage (all pins) C0.5 0.8 v v ih input high voltage 0.2 v cc +1 v cc + 0.5 v v il 1 input low voltage xtal1 C0.5 0.3 v cc v v ih 1 input high voltage xtal1 0.7 v cc v cc + 0.5 v v ol output low voltage (output configured as complementary) (note 3,6) 0.3 0.45 1.5 v v v i ol = 200 a i ol = 3.2 ma i ol = 7.0 ma v oh output high voltage (output configured as complementary) (note 6) v cc C 0.3 v cc C 0.7 v cc C 1.5 v v v i oh = C200 a i oh = C3.2 ma i oh = C7.0 ma v ol 1 output low voltage on p4. x (output configured as comple- mentary) 0.45 0.6 v v i ol = 10 ma i ol = 15 ma notes: 1. typical values are based on a limited number of samples and are not guaranteed. the values listed are at room temperature with v cc = 5.0 v. 2. for temperatures below 100 c , typical is 10 a. 3. for all pins except p4.3:0, which have higher drive capability (see v ol 1 ). 4. for all pins that were weakly pulled high during reset. this excludes ale, inst, and nmi, which were weakly pulled low (see v ol 2 ) and once, which was pulled medium low (see v ol 3 ). 5. pin capacitance is not tested. c s is based on design simulations. 6. during normal (non-transient) conditions, the following maximum current limits apply for pin groups and individual pins: group i ol (ma) i oh (ma) p1 42 42 p2 42 42 p3 42 42 p4 45 21 eport 21 21 individual p1, p2, p3 10 10 p4 18 10
8xc196np commercial chmos 16-bit microcontroller 19 v ol 2 output low voltage in reset on ale, inst, and nmi 0.45 v i ol = 3 a v oh 1 output high voltage in reset (note 4) v cc C 0.7 v i oh = C3 a v ol 3 output low voltage in reset for once pin 0.45 v i ol = 30 a v ol 4 output low voltage on xtal2 0.3 0.45 1.5 v v v i ol = 100 a i ol = 700 a i ol = 3 ma v oh 2 output high voltage on xtal2 v cc C 0.3 v cc C 0.7 v cc C 1.5 v v v i oh = C100 a i oh = C700 a i oh = C3 ma v th + Cv th C hysteresis voltage width on reset# pin 0.3 v c s pin capacitance (any pin to v ss ) (note 5) 10 pf r rst reset pull-up resistor 9 95 k w v cc = 5.5 v, v in = 4.0 v table 9. dc characteristics at v cc = 4.5 C 5.5 v (note 1) (continued) symbol parameter min ty p max units test conditions notes: 1. typical values are based on a limited number of samples and are not guaranteed. the values listed are at room temperature with v cc = 5.0 v. 2. for temperatures below 100 c , typical is 10 a. 3. for all pins except p4.3:0, which have higher drive capability (see v ol 1 ). 4. for all pins that were weakly pulled high during reset. this excludes ale, inst, and nmi, which were weakly pulled low (see v ol 2 ) and once, which was pulled medium low (see v ol 3 ). 5. pin capacitance is not tested. c s is based on design simulations. 6. during normal (non-transient) conditions, the following maximum current limits apply for pin groups and individual pins: group i ol (ma) i oh (ma) p1 42 42 p2 42 42 p3 42 42 p4 45 21 eport 21 21 individual p1, p2, p3 10 10 p4 18 10
8xc196np commercial chmos 16-bit microcontroller 20 figure 5. i cc , i idle versus frequency a3080-01 i cc , i idle vs. frequency frequency (mhz) i cc , i idle (ma) 02468101214161820222426 0 10 20 30 40 50 60 70 80 90 100 i idle @v cc = 5.0 v i cc @v cc = 5.0 v
8xc196np commercial chmos 16-bit microcontroller 21 ac characteristics multiplexed bus mode test conditions: capacitive load on all pins = 50 pf, rise and fall times = 3 ns. table 10. ac characteristics, multiplexed bus mode symbol parameter v cc = 4.5 v C 5.5 v units min max the 8xc196np will meet these specifications f xtal 1 input frequency on xtal1 8 25 mhz t xtal 1 period, 1/f xtal 1 40 125 ns t xhch xtal1 high to clkout high/low 10 110 ns t clcl clkout cycle time 2t xtal 1 ns t chcl clkout high period t xtal 1 C 10 t xtal 1 + 10 ns t avrl ad15:0 valid to rd# low 2t xtal 1 C 20 ns t avwl ad15:0 valid to wr# low 2t xtal 1 C 10 ns t w hsh a19:16, cs x # hold after wr# rising edge 0 t rhsh a19:16, cs x # hold after rd# rising edge 0 t cllh clkout low to ale high C10 10 ns t llch ale low to clkout high C15 10 ns t lhlh ale cycle time 4t xtal 1 ns (2) t lhll ale high period t xtal 1 C 10 t xtal 1 + 10 ns t avll ad15:0 valid to ale low t xtal 1 C15 ns t llax ad15:0 hold after ale low t xtal 1 C 25 ns t llrl ale low to rd# low t xtal 1 C 15 ns t rlcl rd# low to clkout low 0 20 ns t rlrh rd# low period t xtal 1 ns (2) t rhlh rd# high to ale high t xtal 1 C 5 t xtal 1 + 15 ns (3) t rlaz rd# low to address float 5 ns t llwl ale low to wr# low t xtal 1 C 15 ns t clwl clkout low to wr# low C15 10 ns t qvwh data valid before wr# high t xtal 1 C 15 ns (2) t chwh clkout high to wr# high C10 10 ns t wlwh wr# low period t xtal 1 C 5 ns (2) notes: 1. exceeding the maximum specification causes additional wait states. 2. if wait states are used, add 2t xtal 1 n , where n = number of wait states. 3. assuming back-to-back bus cycles. 4. 8-bit bus only.
8xc196np commercial chmos 16-bit microcontroller 22 t whqx data hold after wr# high t xtal 1 C 20 ns t whlh wr# high to ale high t xtal 1 C 12 t xtal 1 + 20 ns (3) t whbx bhe#, inst hold after wr# high t xtal 1 C 10 ns t whax ad15:8 hold after wr# high t xtal 1 C 10 ns (4) t rhbx bhe#, inst hold after rd# high t xtal 1 C 10 ns t rhax ad15:8 hold after rd# high t xtal 1 C 10 ns (4) table 11. ac characteristics, multiplexed bus mode symbol parameter v cc = 4.5 v C 5.5 v units min max the external memory system must meet these specifications t avyv ad15:0 valid to ready setup 2t xtal 1 C 50 ns t ylyh non ready time no upper limit ns t clyx ready hold after clkout low 0 t xtal 1 C 10 ns (1) t avdv ad15:0 valid to input data valid 3t xtal 1 C 40 ns (2) t rldv rd# active to input data valid t xtal 1 C 20 ns (2) t sldv chip-select low, a19:16 valid to data valid 4t xtal 1 C 50 t cldv clkout low to input data valid t xtal 1 C 35 ns t rhdz end of rd# to input data float t xtal 1 C 5 ns t rxdx data hold after rd# inactive 0 ns notes: 1. exceeding the maximum specification causes additional wait states. 2. if wait states are used, add 2t xtal 1 n , where n = number of wait states. table 10. ac characteristics, multiplexed bus mode (continued) symbol parameter v cc = 4.5 v C 5.5 v units min max the 8xc196np will meet these specifications notes: 1. exceeding the maximum specification causes additional wait states. 2. if wait states are used, add 2t xtal 1 n , where n = number of wait states. 3. assuming back-to-back bus cycles. 4. 8-bit bus only.
8xc196np commercial chmos 16-bit microcontroller 23 system bus timings, multiplexed bus figure 6. system bus timing diagram (multiplexed bus mode) clkout ale rd# ad15:0 (read) wr# ad15:0 (write) bhe#, inst ad15:8 t clcl address out data data out address out address out t chcl t lhll valid a2844-01 t cllh t rlcl t llch t lhlh t llrl t rlrh t rhlh t avll t llax t rldv t rhdz t rlaz address out t avdv t llwl t wlwh t whlh t qvwh t whqx t rhbx t whbx t rhax t whax t sldv a19:16 cs x # address out t whsh t rhsh xtal1 t xhch t xtal1
8xc196np commercial chmos 16-bit microcontroller 24 ready timing, multiplexed bus figure 7. ready timing diagram (multiplexed bus mode) t0016-02 t wlwh + 2t xtal1 t qvwh + 2t xtal1 t clyx (max) t avyv t lhlh + 2t xtal1 t rlrh + 2t xtal1 t avdv + 2t xtal1 t rldv + 2t xtal1 address out data in address out data out clkout ready ale rd# ad15:0 wr# ad15:0 bhe#, inst a19:16 cs x # t clyx (min) (read) (write) valid extended addr ess out valid
8xc196np commercial chmos 16-bit microcontroller 25 ac characteristics demultiplexed bus mode test coditions: capacitive load on all pins = 50 pf, rise and fall times = 3 ns. table 12. ac characteristics, demultiplexed bus mode symbol parameter v cc = 4.5 v C 5.5 v units min max the 8xc196np will meet these specifications f xtal 1 input frequency on xtal1 8 25 mhz t xtal 1 period, 1/f xtal 1 40 125 ns t xhch xtal1 high to clkout high/low 10 110 ns t clcl clkout cycle time 2t xtal 1 ns t chcl clkout high period t xtal 1 C 10 t xtal 1 + 10 ns t avrl a19:0, cs x # valid to rd# low 2t xtal 1 C 30 ns t avwl a19:0, cs x # valid to wr# low 2t xtal 1 C 25 ns t cllh clkout low to ale high C 10 10 ns t llch ale low to clkout high C 15 10 ns t lhlh ale cycle time 4t xtal 1 ns (2) t lhll ale high period t xtal 1 C 10 t xtal 1 + 10 ns t avll address valid to ale low na ns t llax address hold after ale low na ns t llrl ale low to rd# low na ns t rlch rd# low to clkout high 0 15 ns t rlrh rd# low period 2t xtal 1 C 10 ns (2) t rhlh rd# high to ale high t xtal 1 C 5 t xtal 1 + 20 ns (3) t rlaz rd# low to address float na ns t llwl ale low to wr# low na ns t wlch wr# low to clkout high C 5 10 ns t qvwh data valid before wr# high 3t xtal 1 C 37 ns (2) t chwh clkout high to wr# high C 15 5 ns t wlwh wr# low period 2t xtal 1 C 10 ns (2) t whqx data hold after wr# high t xtal 1 C 20 ns t whlh wr# high to ale high t xtal 1 C 5 t xtal 1 + 20 ns (3) t whbx bhe#, inst hold after wr# high t xtal 1 C 10 ns notes: 1. exceeding the maximum specification causes additional wait states. 2. if wait states are used, add 2t xtal 1 n , where n = number of wait states. 3. assuming back-to-back bus cycles.
8xc196np commercial chmos 16-bit microcontroller 26 t whax a19:0, cs x # hold after wr# high 0 ns t rhbx bhe#, inst hold after rd# high t xtal 1 C 10 ns t rhax a19:0, cs x # hold after rd# high 0 ns table 13. ac characteristics, demultiplexed bus mode symbol parameter v cc = 4.5 v C 5.5 v units min max the external memory system must meet these specifications t avyv a19:0, cs x # valid to ready setup 3t xtal 1 C 60 ns t ylyh non ready time no upper limit ns t clyx ready hold after clkout low 0 t xtal 1 C 10 ns (1) t avdv a19:0, cs x # valid to input data valid 4t xtal 1 C 50 ns (2) t rldv rd# active to input data valid 2t xtal 1 C 25 ns (2) t cldv clkout low to input data valid t xtal 1 C 35 ns t rhdz end of rd# to input data float t xtal 1 C 5 ns t rxdx data hold after rd# inactive 0 ns notes: 1. exceeding the maximum specification causes additional wait states. 2. if wait states are used, add 2t xtal 1 n , where n = number of wait states. table 12. ac characteristics, demultiplexed bus mode (continued) symbol parameter v cc = 4.5 v C 5.5 v units min max the 8xc196np will meet these specifications notes: 1. exceeding the maximum specification causes additional wait states. 2. if wait states are used, add 2t xtal 1 n , where n = number of wait states. 3. assuming back-to-back bus cycles.
8xc196np commercial chmos 16-bit microcontroller 27 system bus timings, demultiplexed bus figure 8. system bus timing diagram (demultiplexed bus mode) clkout ale rd# ad15:0 (read) wr# ad15:0 (write) bhe#, inst a19:0 cs x # t clcl valid valid address out t chcl t lhll valid a2845-01 t cllh t cldv t llch t lhlh t rlch t rlrh t rhlh t rldv t rhdz t avdv t wlch t wlwh t whlh t qvwh t whqx t rhbx t whbx t rhax t whax t chwh address xtal1 t xtal1 t xhch
8xc196np commercial chmos 16-bit microcontroller 28 ready timing, demulti plexed bus figure 9. ready timing diagram (demultiplexed bus mode) t0015-02 t clyx (max) t avdv + 2t xtal1 t wlwh + 2t xtal1 t avyv t lhlh + 2t xtal1 t rlrh + 2t xtal1 t rldv + 2t xtal1 t qvwh + 2t xtal1 data data out clkout ready ale rd# ad15:0 wr# ad15:0 bhe#, inst a19:0 cs x # t clyx (min) (read) (write) valid extended addr ess out valid
8xc196np commercial chmos 16-bit microcontroller 29 hold#/hlda# timing figure 10. hold#/hlda# timing diagram table 14. hold#/hlda# timings symbol parameter v cc = 4.5 v C 5.5 v units min max t hvch hold# setup time 65 ns (1) t clhal clkout low to hlda# low C15 15 ns t clbrl clkout low to breq# low C15 15 ns t halaz hlda# low to address float 33 ns t halbz hlda# low to bhe#, inst, rd#, wr# weakly driven 25 ns t clhah clkout low to hlda# high C25 15 ns t clbrh clkout low to breq# high C25 25 ns t hahax hlda# high to address no longer float C20 ns t hahbv hlda# high to bhe#, inst, rd#, wr# valid C20 ns note: 1. to guarantee recognition at next clock. a2460-03 clkout hold# hlda# breq# a19:0, ad15:0 cs x #, bhe#, inst, rd#, wr# wrl#, wrh# ale t cllh t clhah t clbrh t hahax t hahbv t halbz t halaz t clbrl t clhal t hvch t hvch hold latency start of strongly driven ale weakly held inactive
8xc196np commercial chmos 16-bit microcontroller 30 ac characteristics serial port, shift register mode figure 11. serial port waveform shift register mode table 15. serial port timing shift register mode symbol parameter v cc = 4.5 v C 5.5 v units min max t xlxl serial port clock period (sp_baud 3 x 002h) (sp_baud = x 001h) (note 1) 6t xtal 1 4t xtal 1 ns ns t qvxh output data setup to clock high 3t xtal 1 ns t xhqx output data hold after clock high 2t xtal 1 C 50 ns t xhqv next output data valid after clock high 2t xtal 1 + 50 ns t dvxh input data setup to clock high 2t xtal 1 + 200 ns t xhdx input data hold after clock high 0 ns t xhqz last clock high to output float 5t xtal 1 ns note: 1. the minimum baud-rate register (sp_ baud) value for receive is x 002h and the minimum baud-rate register value for transmit is x 001h. valid valid valid valid valid valid valid valid rxd (in) (out) txd 01 2 3 4 5 6 7 t qvxh t xlxl t dvxh t xhqv t xhqz t xhdx t xhqx t xlxh a2080-02 rxd
8xc196np commercial chmos 16-bit microcontroller 31 external clock drive figure 12. external clock drive waveforms figure 13. ac testing output waveforms during 5.0 volt testing table 16. external clock drive symbol parameter min max units 1/t xlxl input frequency 8 25 mhz t xlxl period (t xtal 1 )40125ns t xhxx high time 0.35t xtal 1 0.65t xtal 1 ns t xlxx low time 0.35t xtal 1 0.65t xtal 1 ns t xlxh rise time 10 ns t xhxl fall time 10 ns a2119-02 t xhxx t xlxx t xhxl t xlxl 0.3 v cc C 0.5 v 0.7 v cc + 0.5 v t xlxh 0.7 v cc + 0.5 v 0.3 v cc C 0.5 v test points 2.0 v 0.8 v ac testing inputs are driven at 3.5 v for a logic "1" and 0.45 v for a logic "0". timing measurements are made at 2.0 v for a logic "1" and 0.8 v for a logic "0". 3.5 v 0.45 v a2120-02 2.0 v 0.8 v
8xc196np commercial chmos 16-bit microcontroller 32 figure 14. float waveforms during 5.0 volt testing explanation of ac symbols each ac timing symbol is two pairs of letters prefixed by t for time. the characters in a pair indicate a signal and its condition, respectively. symbols represent the time between the two signal/condition points. conditions: signals: h high a address l ale/adv# l low ad address/data bus for br breq# multiplexed bus mode v valid b bhe# r rd# x no longer valid c clkout w wr#/wrh#/wrl# z floating d data x xtal1 g buswidth y ready h hold# q data out ha hlda# s chip select v load + 0.15 v v load C 0.15 v timing reference points v load v oh C 0.15 v v ol + 0.15 v for timing purposes, a port pin is no longer floating when a 150 mv change from load voltage occurs and begins to float when a 150 mv change from the loading v oh /v ol level occurs with i ol /i oh 15 ma. a2121-01
8xc196np commercial chmos 16-bit microcontroller 33 8xc196np errata change identifiers have been used on embedded products since 1990. the change identifier is the last character in the fpo number. the fpo number is typically a nine character number located on the second line of the topside package mark. the following errata listing is applicable to the bCstep (denoted by a b or c at the end of the topside tracking number): 1. any jump, conditional jump, or call instruction located within six bytes of the top of a page, i.e., 0fffaC0ffffh, may cause a jump to the wrong page. to ensure this problem does not occur, place at least six nops at the top of each page. the following errata listing is applicable to the aC step (denoted by an a at the end of the topside tracking number): 1. any jump, conditional jump, or call instruction located within six bytes of the top of a page, i.e., 0fffaC0ffffh, may cause a jump to the wrong page. to ensure this problem does not occur, place at least six nops at the top of each page. 2. the illegal opcode interrupt vector is not taken when an illegal opcode is encountered. a branch to an unknown location occurs. 3. (1-mbyte mode only.) if an interrupt is aborted, intentionally or unintentionally, an undesired branch to the lowest priority interrupt vector (ff2000h) may occur even if the lowest priority interrupt is not enabled. this may occur if any bit in the int_mask, int_mask1, int_pend, or int_pend1 register is cleared after the corresponding int_pend or int_pend1 bit is set. 4. (1-mbyte mode only.) if a standard interrupt occurs at approximately the same time (this time is code dependent and therefore cannot be stated as an exact number of state times) as a pts serviced interrupt, the pts interrupt may be processed as a standard interrupt. the standard interrupt service routine for a pts serviced interrupt (end-of-pts) is typically used to modify the pts control block and re- enable the pts by setting the corresponding bit in the ptssel register. when this anomaly occurs, the end-of-pts service routine will execute regardless of the value in ptscount. as a result, an undetermined number of pts cycles will not occur. this applies to all pts interrupts. data sheet revision history this data sheet is valid for devices with a b at the end of the topside tracking number. data sheets are changed as new device information becomes available. verify with your local intel sales office that you have the latest version before finalizing a design or ordering devices. the following are important changes to the 272459- 005 datasheet: 1. revised tables 8 through 15 and figures 5, 6, 7, and 13 to reflect new or changed informa- tion. 2. added table 3 and figure 9. 3. the input frequency on xtal1, formerly called f osc , is now denoted by f xtal 1 . 4. the ac characteristics tables have been divided into the following: the timing specifica- tions met by the device, and the timing specifi- cations that must be met by the external memory system. 5. maximum iol and ioh specifications added to the dc characteristics tables. 6. ac timings t avwl and t avrl added to the ac characteristicsCmultiplexed bus mode tables.
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